1. Field of the Invention
The present invention relates to a solid-state image sensor, a production method therefor, and a camera using a solid-state image sensor. More particularly, the present invention relates to a solid-state image sensor having a signal amplifier in each pixel, a production method therefor, and a camera including such an image sensor.
2. Description of the Related Art
Typical examples of solid-state image sensors are CCD sensors including photodiodes and CCD shift registers, and CMOS sensors in which a pixel section is constituted by active pixels each composed of a photodiode and an MOS transistor. CMOS sensors have the following advantages over CCD sensors:    (1) The power consumption is low.    (2) Since peripheral circuits can be mounted on a single chip, a signal-processing circuit can be provided on the same chip, and compact solid-state image sensors can be produced at low cost.    (3) Since the process design can be made based on a known MOS process, solid-state image sensors can be provided without using a special production line.
In order to obtain the above advantages, it is preferable that the power voltage does not substantially deviate from, for example, 5 V or 3.3 V that is standardized in the normal CMOS process. For this reason, there is a restriction on the gate voltage during a transfer operation for reading signal charges accumulated in a photodiode in each pixel, and it is not always easy to design a transfer structure for the signal charges accumulated in the photodiode. In particular, when a buried photodiode structure is adopted to limit dark current, and when a photodiode is completely depleted at the time of reset, in order to cancel the influence of reset noise, a structure for transferring charges in the photodiode cannot be easily achieved.
This problem will be described with reference to FIG. 7, which graphically illustrates a known solid-state image sensor. Referring to FIG. 7, the solid-state image sensor includes, in each pixel, a semiconductor substrate 701, a well 702 made of a p-type semiconductor in an image pickup region, a transfer gate 703 for transferring signal charges accumulated in a pixel to a diffusion region 704, a gate oxide 705, a p-type high-concentration layer 706, and an accumulation region 707 of a photodiode that is made of an n-type semiconductor and that is covered with the p-type high-concentration layer 706. The p-type high-concentration layer 706 is provided to prevent a depletion layer extending from the accumulation region 707 from reaching the gate oxide 705, and to thereby limit dark current. In such a buried photodiode, when being transferred to the diffusion region 704, charges in the accumulation region 707 must be transferred from a position deeply recessed from the gate oxide 705. In order to enable such transfer, a charge-transfer region 708 is provided. The gate voltage necessary for transfer is restricted by the concentration and width of the charge-transfer region 708. That is, as long as the concentration and width of the charge-transfer region 708 are satisfactory, the charges in the photodiode can be completely transferred at a desired power voltage, the photodiode can be completely reset, and the signal charges can be completely transferred.
A method for forming the above-described structure is proposed in Japanese Patent Laid-Open No. 11-274454. The abstract and example of the proposal will be described briefly as follows:    (1) Stable production is allowed by forming a charge-transfer region with respect to a transfer gate in a self-alignment manner.    (2) The charge transfer region can be formed by thermally diffusing phosphorus as an ion species at the angle shown by arrow 709 in FIG. 7 during ion implantation for an accumulation region.    (3) As an example, an n-layer (accumulation region) and a charge-transfer region in the photodiode are formed by two ion implantation operations that are different in angle and energy. This can optimize the characteristics.
A structure capable of complete transfer can be achieved by forming a wide, high-concentration charge-transfer region by the above method. In this case, however, the following problem occurs. When the concentration and width of the charge-transfer region are excessively large, a depletion layer of the photodiode reaches the interface of a gate oxide during accumulation, in spite of the buried photodiode structure for reducing dark current, and dark current markedly increases. In order to solve this problem, an inversion layer is formed on the charge-transfer region by decreasing the voltage of the transfer gate electrode below the well voltage during accumulation (hereinafter, referred to as “transfer-gate low-level voltage”), as disclosed in Japanese Patent Laid-Open No. 2001-245216.
As described above, in the technique disclosed in Japanese Patent Laid-Open No. 11-274454, when the concentration and width of the charge transfer region are excessively large, a depletion layer of the photodiode reaches the interface of the gate oxide during accumulation, in spite of the buried photodiode structure for reducing dark current, and dark current markedly increases.
While the method disclosed in Japanese Patent Laid-Open No. 2001-245216 is highly effective, it is preferable, for lower power consumption and lower voltage, that the low-level voltage of the transfer gate be as close to the well voltage as possible.